1. Field of the Invention
The present invention relates to a memory apparatus, and more particularly, to a memory apparatus including a memory device having a gate insulating layer formed by stacking a tunnel oxide layer, a charge trap layer, and a block oxide layer, and a gate electrode formed on the block oxide layer.
2. Description of the Related Art
Conventional memory apparatuses include a memory device having a gate insulating layer formed by stacking three layers, that is, a tunnel oxide layer, a charge trap layer, and a block oxide layer, and a gate electrode formed on the block oxide layer. Referring to FIG. 6, such a conventional memory apparatus including a silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a gate insulating layer 15 having a structure in which a tunnel oxide layer 12 that is formed as an oxide layer, a charge trap layer 13 that is formed as a nitride layer, and a block oxide layer 14 that is formed as an oxide layer, are sequentially stacked on a silicon (Si) substrate 11, and a polysilicon gate electrode 16 formed on the gate insulating layer 15 (i.e., see Patent Documents 1 & 2).
In a SONOS memory device, a silicon oxide layer (SiO2 layer) or an alumina layer (Al2O3 layer) is used as a block oxide layer. The band structure of a memory apparatus including such a SONOS memory device is shown in FIG. 7.    [Patent Document 1]: Japanese Laid-Open Patent Publication No. 2001-358237    [Patent Document 2]: Japanese Laid-Open Patent Publication No. 2002-280467
In a conventional memory apparatus including a SONOS memory device, there is a problem that data erase speed is slow and a data erase operation is incomplete. This is because, when electrons accumulated in a charge trap layer are emitted toward a substrate by applying a high negative voltage to a gate electrode during a data erase operation, electrons are newly injected into the charge trap layer from the gate electrode.
FIG. 8 illustrates a band structure of a SONOS memory device when a negative voltage is applied to a gate electrode during a data erase operation. The structure of a SONOS model used in calculation of the band structure of FIG. 8 is constituted by:
gate electrode work function (Φm)=5 eV
block oxide layer: SiO2 layer, thickness of 7 nm
charge trap layer: Si3N4 layer, thickness of 4 nm
tunnel oxide layer: SiO2 layer, thickness of 3.5 nm
erase voltage (Vg−Vfb)=18 V
Referring to FIG. 8, when the negative voltage is applied to the gate electrode, an insulating layer has a large gradient with respect to potential, and the height and thickness of a barrier wall seen from electrons accumulated on the gate electrode decrease. The block oxide layer is a barrier wall that suppresses injection of electrons from the gate electrode, but in a conventional SONOS memory device including a block oxide layer formed of a silicon oxide layer or alumina, electron injection is not sufficiently suppressed.